178 search results - page 31 / 36 » Power Compiler: A Gate-Level Power Optimization and Synthesi... |
DAC
2006
ACM
14 years 9 months ago
2006
ACM
Pareto surfaces in the performance space determine the range of feasible performance values for a circuit topology in a given technology. We present a non-dominated sorting based ...
ISLPED
2004
ACM
14 years 2 months ago
2004
ACM
Microprocessor designers use techniques such as clock gating to reduce power dissipation. An unfortunate side-effect of these techniques is the processor current fluctuations th...
IEEEPACT
2002
IEEE
14 years 1 months ago
2002
IEEE
Modern embedded systems often require high degrees of instruction-level parallelism (ILP) within strict constraints on power consumption and chip cost. Unfortunately, a high-perfo...
VLSID
2002
IEEE
14 years 9 months ago
2002
IEEE
If motion estimation can choose the most suitable algorithm according to the changing characteristics of input image signals, we can get benefits, which improve quality and perfor...
ICCAD
2008
IEEE
14 years 5 months ago
2008
IEEE
— Leveraging the power of scratchpad memories (SPMs) available in most embedded systems today is crucial to extract maximum performance from application programs. While regular a...