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ICCD
2003
IEEE
143views Hardware» more  ICCD 2003»
14 years 1 months ago
Aggressive Test Power Reduction Through Test Stimuli Transformation
Excessive switching activity during shift cycles in scan-based cores imposes considerable test power challenges. To ensure rapid and reliable test of SOCs, we propose a scan chain...
Ozgur Sinanoglu, Alex Orailoglu
DSD
2005
IEEE
106views Hardware» more  DSD 2005»
14 years 2 months ago
Power-Constrained Hybrid BIST Test Scheduling in an Abort-on-First-Fail Test Environment
1 This paper presents a method for power-constrained system-on-chip test scheduling in an abort-on-first-fail environment where the test is terminated as soon as a fault is detecte...
Zhiyuan He, Gert Jervan, Zebo Peng, Petru Eles
MTV
2007
IEEE
118views Hardware» more  MTV 2007»
14 years 2 months ago
Reduction of Power Dissipation during Scan Testing by Test Vector Ordering
Test vector ordering is recognized as a simple and non-intrusive approach to assist test power reduction. Simulation based test vector ordering approach to minimize circuit transit...
Wang-Dauh Tseng, Lung-Jen Lee
CSDA
2011
13 years 3 months ago
An affine invariant multiple test procedure for assessing multivariate normality
: A multiple test procedure for assessing multivariate normality (MVN) that combines a finite set of affine invariant test statistics for MVN is proposed. This combination is base...
Carlos Tenreiro