Sciweavers

1419 search results - page 8 / 284
» Power Droop Testing
Sort
View
ICCAD
2010
IEEE
133views Hardware» more  ICCAD 2010»
13 years 7 months ago
Testing methods for detecting stuck-open power switches in coarse-grain MTCMOS designs
Coarse-grain multi-threshold CMOS (MTCMOS) is an effective power-gating technique to reduce IC's leakage power consumption by turning off idle devices with MTCMOS power switc...
Szu-Pang Mu, Yi-Ming Wang, Hao-Yu Yang, Mango Chia...
HICSS
1998
IEEE
94views Biometrics» more  HICSS 1998»
14 years 2 months ago
An Internet-Based Platform for Testing Generation Scheduling Auctions
This paper describes the uses and architecture of a network-centered computing-rich software platform called PowerWeb. PowerWeb was designed and built as a simulation environment ...
Ray Zimmerman, Robert J. Thomas, Deqiang Gan, Carl...
EVOW
1999
Springer
14 years 2 months ago
Test Pattern Generation Under Low Power Constraints
A technique is proposed to reduce the peak power consumption of sequential circuits during test pattern application. High-speed computation intensive VLSI systems, as telecommunica...
Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Re...
VTS
1998
IEEE
124views Hardware» more  VTS 1998»
14 years 2 months ago
A Test Pattern Generation Methodology for Low-Power Consumption
This paper proposes an ATPG technique that reduces power dissipation during the test of sequential circuits. The proposed approach exploits some redundancy introduced during the t...
Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo,...
ATS
2005
IEEE
118views Hardware» more  ATS 2005»
14 years 3 months ago
Partial Gating Optimization for Power Reduction During Test Application
Power reduction during test application is important from the viewpoint of chip reliability and for obtaining correct test results. One of the ways to reduce scan test power is to...
Mohammed ElShoukry, Mohammad Tehranipoor, C. P. Ra...