296 search results - page 29 / 60 » Power Estimation in Sequential Circuits |
ISLPED
2003
ACM
14 years 1 months ago
2003
ACM
This paper addresses two aspects of low-power design for FPGA circuits. First, we present an RT-level power estimator for FPGAs with consideration of wire length. The power estima...
ASPDAC
2004
ACM
14 years 1 months ago
2004
ACM
— Reducing the ever-growing leakage power is critical to power efficient designs. Leakage reduction techniques such as power-gating using sleep transistor insertion introduces la...
ISPD
2004
ACM
14 years 1 months ago
2004
ACM
High performance integrated circuits are now reaching the 100-plus watt regime, and power delivery and power grid signal integrity have become critical. Analyzing the performance ...
ISLPED
1995
ACM
13 years 11 months ago
1995
ACM
This paper presents an e ective multiple clocking scheme for lower power RTL circuit design. The basis is to partition a behavioral description of the circuit into m modules fed b...
ICCAD
1998
IEEE
14 years 8 days ago
1998
IEEE
Retiming and resynthesis transformations can be used for optimizing the area, power, and delay of sequential circuits. Even though this technique has been known for more than a de...