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JCSC
2002
87views more  JCSC 2002»
13 years 11 months ago
Power Estimator Development for Embedded System Memory Tuning
Memory accesses account for a large percentage of total power in microprocessor-based embedded systems. The increasing use of microprocessor cores and synthesis, rather than prefa...
Frank Vahid, Tony Givargis, Susan Cotterell
ISSS
2002
IEEE
151views Hardware» more  ISSS 2002»
14 years 4 months ago
Tuning of Loop Cache Architectures to Programs in Embedded System Design
Adding a small loop cache to a microprocessor has been shown to reduce average instruction fetch energy for various sets of embedded system applications. With the advent of core-b...
Frank Vahid, Susan Cotterell
GLVLSI
2007
IEEE
172views VLSI» more  GLVLSI 2007»
14 years 5 months ago
The effect of temperature on cache size tuning for low energy embedded systems
Energy consumption is a major concern in embedded computing systems. Several studies have shown that cache memories account for about 40% or more of the total energy consumed in t...
Hamid Noori, Maziar Goudarzi, Koji Inoue, Kazuaki ...
DATE
2004
IEEE
147views Hardware» more  DATE 2004»
14 years 2 months ago
Automatic Tuning of Two-Level Caches to Embedded Applications
The power consumed by the memory hierarchy of a microprocessor can contribute to as much as 50% of the total microprocessor system power, and is thus a good candidate for optimiza...
Ann Gordon-Ross, Frank Vahid, Nikil Dutt
ISLPED
2005
ACM
150views Hardware» more  ISLPED 2005»
14 years 4 months ago
Fast configurable-cache tuning with a unified second-level cache
Tuning a configurable cache subsystem to an application can greatly reduce memory hierarchy energy consumption. Previous tuning methods use a level one configurable cache only, or...
Ann Gordon-Ross, Frank Vahid, Nikil D. Dutt