430 search results - page 10 / 86 » Power Optimized Combinational Logic Design |
GLVLSI
2007
IEEE
14 years 2 months ago
2007
IEEE
A probabilistic power estimation technique for combinational circuits is presented. A novel set of simple waveforms is the kernel of this technique. The transition density of each...
VTS
2006
IEEE
14 years 1 months ago
2006
IEEE
Abstract: An optimization algorithm for the design of combinational circuits that are robust to single-event upsets (SEUs) is described. A simple, highly accurate model for the SEU...
DAC
2003
ACM
14 years 8 months ago
2003
ACM
As power consumption of the clock tree in modern VLSI designs tends to dominate, measures must be taken to keep it under control. This paper introduces an approach for reducing cl...
ISLPED
2004
ACM
14 years 1 months ago
2004
ACM
The need to perform early design studies that combine architectural simulation with power estimation has become critical as power has become a design constraint whose importance h...
GECCO
2005
Springer
14 years 1 months ago
2005
Springer
This paper proposes and analyses the performance of a Genetic Algorithm (GA) using two new concepts, namely a static fitness function including a discontinuity measure and a fract...