430 search results - page 12 / 86 » Power Optimized Combinational Logic Design |
DAC
2006
ACM
14 years 8 months ago
2006
ACM
Subthreshold circuit designs have been demonstrated to be a successful alternative when ultra-low power consumption is paramount. However, the characteristics of MOS transistors i...
VLSID
2002
IEEE
14 years 8 months ago
2002
IEEE
Compare CMOS Logic with Pass-Transistor Logic, a question was raised in our mind: "Does any rule exist that contains all good?" This paper reveals novel logic synthesis ...
ARITH
2003
IEEE
14 years 1 months ago
2003
IEEE
We propose a split array multiplier organized in a left-to-right leapfrog (LRLF) structure with reduced delay compared to conventional array multipliers. Moreover, the proposed de...
ISCA
2000
IEEE
14 years 2 days ago
2000
IEEE
As microprocessors continue to evolve, many optimizations reach a point of diminishing returns. We introduce HLS, a hybrid processor simulator which uses statistical models and sy...
POPL
1994
ACM
13 years 11 months ago
1994
ACM
ions of abstract domains for logic programming: open product and generic pattern construction Agostino Cortesia; , Baudouin Le Charlierb , Pascal Van Hentenryckc aDipartimento di I...