430 search results - page 28 / 86 » Power Optimized Combinational Logic Design |
ICCD
2005
IEEE
14 years 7 months ago
2005
IEEE
The dynamic instruction scheduling logic is one of the most critical components of modern superscalar microprocessors, both from the delay and power dissipation standpoints. The d...
WCNC
2008
IEEE
14 years 4 months ago
2008
IEEE
— Weather attenuations can have a distorting effect on signal fidelity above 10 GHz that lead to excessive digital transmission error. This loss of signal is commonly referred to...
CEC
2003
IEEE
14 years 3 months ago
2003
IEEE
In this paper, the use of Simulated Evolution (SimE) Algorithm in the design of digital logic circuits is proposed. SimE algorithm consists of three steps: evaluation, selection an...
DAC
2006
ACM
14 years 11 months ago
2006
ACM
Design and verification of systems at the Register-Transfer (RT) or behavioral level require the ability to reason at higher levels of abstraction. Difference logic consists of an...
DAC
2004
ACM
14 years 11 months ago
2004
ACM
Power consumption, particularly runtime leakage, in long on-chip buses has grown to an unacceptable portion of the total power budget due to heavy buffer insertion to combat RC de...