430 search results - page 32 / 86 » Power Optimized Combinational Logic Design |
IEEEPACT
2008
IEEE
14 years 4 months ago
2008
IEEE
The emergence of power as a first-class design constraint has fueled the proposal of a growing number of run-time power optimizations. Many of these optimizations trade-off power...
DATE
2009
IEEE
14 years 2 months ago
2009
IEEE
In the digital VLSI cycle, logic transformations are often required to modify the design to meet different synthesis and optimization goals. Logic transformations on sequential ci...
VLSID
2002
IEEE
14 years 3 months ago
2002
IEEE
We propose a timing-oriented logic optimization technique called Generalized De Morgan (GDM) transform, that integrates gate resizing, net buffering and De Morgan transformation. ...
DAC
2009
ACM
14 years 11 months ago
2009
ACM
Embedded cryptosystems show increased vulnerabilities to implementation attacks such as power analysis. CMOS technology trends are causing increased process variations which impac...
DATE
1998
IEEE
14 years 2 months ago
1998
IEEE
As the "system-on-a-chip" concept is rapidly becoming a reality, time-to-market and product complexity push the reuse of complex macromodules. Circuits combining a varie...