430 search results - page 33 / 86 » Power Optimized Combinational Logic Design |
DAC
1997
ACM
14 years 2 months ago
1997
ACM
We describe an architectural design space exploration methodology that minimizes the energy dissipation of digital circuits. The centerpiece of our methodology is a Verilog-based ...
ICCD
2002
IEEE
14 years 7 months ago
2002
IEEE
Power is considered to be the major limiter to the design of more faster and complex processors in the near future. In order to address this challenge, a combination of process, c...
ISCA
2005
IEEE
14 years 3 months ago
2005
IEEE
One of the most important problems faced by microarchitecture designers is the poor scalability of some of the current solutions with increased clock frequencies and wider pipelin...
CORR
2011
Springer
13 years 5 months ago
2011
Springer
Markov Logic Networks (MLNs) have emerged as a powerful framework that combines statistical and logical reasoning; they have been applied to many data intensive problems including...
FPGA
2003
ACM
14 years 3 months ago
2003
ACM
This paper proposes a new high-level technique for designing fault tolerant systems in SRAM-based FPGAs, without modifications in the FPGA architecture. Traditionally, TMR has bee...