734 search results - page 100 / 147 » Power balanced pipelines |
ASPDAC
2004
ACM
14 years 3 months ago
2004
ACM
– A low-power graphics LSI is designed and implemented for mobile multimedia applications. The LSI contains a 32bit RISC processor with enhanced MAC, a 3D rendering engine, progr...
RTSS
2003
IEEE
14 years 3 months ago
2003
IEEE
This paper presents a quantification of the timing effects that advanced processor features like data and instruction cache, pipelines, branch prediction units and out-oforder ex...
DATE
2010
IEEE
14 years 3 months ago
2010
IEEE
Increasing dynamic variability with technology scaling has made it essential to incorporate large design-time timing margins to ensure yield and reliable operation. Online techniq...
ISCA
2010
IEEE
14 years 3 months ago
2010
IEEE
Previous research has shown that Staged Execution (SE), i.e., dividing a program into segments and executing each segment at the core that has the data and/or functionality to bes...
FCCM
1999
IEEE
14 years 2 months ago
1999
IEEE
Technology scaling of CMOS processes brings relatively faster transistors (gates) and slower interconnects (wires), making viable the addition of reconfigurability to increase per...