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ICCAD
2005
IEEE
127views Hardware» more  ICCAD 2005»
14 years 5 months ago
Flip-flop insertion with shifted-phase clocks for FPGA power reduction
— Although the LUT (look-up table) size of FPGAs has been optimized for general applications, complicated designs may contain a large number of cascaded LUTs between flip-flops...
Hyeonmin Lim, Kyungsoo Lee, Youngjin Cho, Naehyuck...
MICRO
2003
IEEE
143views Hardware» more  MICRO 2003»
14 years 2 months ago
VSV: L2-Miss-Driven Variable Supply-Voltage Scaling for Low Power
Energy-efficient processor design is becoming more and more important with technology scaling and with high performance requirements. Supply-voltage scaling is an efficient way to...
Hai Li, Chen-Yong Cher, T. N. Vijaykumar, Kaushik ...
GLOBECOM
2007
IEEE
14 years 3 months ago
Stability Emphasizing Cross-Layer Optimization of Transmit Power Allocation in Distributed Wireless Networks
Abstract— This paper theoretically analyzes cross-layer optimized design of transmit power allocation in distributed interference-limited wireless networks with asynchronously ac...
Stepán Kucera, Sonia Aïssa, Susumu Yos...
HICSS
2003
IEEE
129views Biometrics» more  HICSS 2003»
14 years 2 months ago
Experimental Studies and Modeling of an Information Embedded Power System
This paper develops a model of an electrical power system, with its inherent embedded communication system, for the purpose of studying the characteristics of power system measure...
Stephen P. Carullo, Chika Nwankpa
PACS
2004
Springer
115views Hardware» more  PACS 2004»
14 years 2 months ago
Reducing Delay and Power Consumption of the Wakeup Logic Through Instruction Packing and Tag Memoization
Dynamic instruction scheduling logic is one of the most critical components of modern superscalar microprocessors, both from the delay and power dissipation standpoints. The delay ...
Joseph J. Sharkey, Dmitry Ponomarev, Kanad Ghose, ...