734 search results - page 7 / 147 » Power balanced pipelines |
CCECE
2011
IEEE
12 years 8 months ago
2011
IEEE
—In this work the design of a low power 10-bit 100MS/s pipeline ADC is presented. Low power consumption is realized by using an optimum bit per stage resolution and also by apply...
ISCAS
2003
IEEE
14 years 1 months ago
2003
IEEE
This paper proposes a low power commutator architecture based on triple port RAMs rather than dual port RAMs or conventional FIFO.forthe radix-4 pipelined FFTprocessor implementat...
TVLSI
2010
13 years 3 months ago
2010
Digital calibration techniques are widely utilized to linearize pipelined analog-to-digital converters (ADCs). However, their power dissipation can be prohibitively high, particula...
ICCAD
1999
IEEE
14 years 26 days ago
1999
IEEE
This paper proposes a new bipatition-codec architecture that may reduce power consumption of pipelined circuits. We treat each output value of a pipelined circuit as one state of ...
MICRO
2003
IEEE
14 years 1 months ago
2003
IEEE
With increasing clock frequencies and silicon integration, power aware computing has become a critical concern in the design of embedded processors and systems-on-chip. One of the...