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CHES
2004
Springer
121views Cryptology» more  CHES 2004»
14 years 2 months ago
Power Analysis of an FPGA: Implementation of Rijndael: Is Pipelining a DPA Countermeasure?
Since their publication in 1998, power analysis attacks have attracted significant attention within the cryptographic community. So far, they have been successfully applied to di...
François-Xavier Standaert, Siddika Berna &O...
GLVLSI
2003
IEEE
152views VLSI» more  GLVLSI 2003»
14 years 1 months ago
Dynamic single-rail self-timed logic structures for power efficient synchronous pipelined designs
The realization of fast datapaths in signal processing environments requires fastest, power efficient logic styles with synchronous behavior. This paper presents a method to combi...
Frank Grassert, Dirk Timmermann
DATE
2006
IEEE
89views Hardware» more  DATE 2006»
14 years 2 months ago
Automatic insertion of low power annotations in RTL for pipelined microprocessors
We propose instruction-driven slicing, a new technique for annotating microprocessor descriptions at the Register Transfer Level (RTL) in order to achieve lower power dissipation....
Vinod Viswanath, Jacob A. Abraham, Warren A. Hunt ...
CSREAESA
2004
13 years 10 months ago
A Low-Power Pipelined Implementation of 2D Discrete Wavelet Transform
Discrete wavelet transform has been incorporated as part of the JPEG2000 image compression standard and is being deployed in various portable consumer products. This raises the in...
Yong Liu, Edmund Ming-Kit Lai, A. Benjamin Premkum...
ISCA
2005
IEEE
166views Hardware» more  ISCA 2005»
14 years 2 months ago
Increased Scalability and Power Efficiency by Using Multiple Speed Pipelines
One of the most important problems faced by microarchitecture designers is the poor scalability of some of the current solutions with increased clock frequencies and wider pipelin...
Emil Talpes, Diana Marculescu