732 search results - page 10 / 147 » Power minimization using control generated clocks |
CSE
2009
IEEE
14 years 3 months ago
2009
IEEE
Abstract—Today’s wirelessly networked embedded systems underlie a vast array of electronic devices, performing computation, communication, and input/output. A major design goal...
ISPD
2004
ACM
14 years 2 months ago
2004
ACM
Modern processors and SoCs require the adoption of poweroriented design styles, due to the implications that power consumption may have on reliability, cost and manufacturability ...
ISLPED
2005
ACM
14 years 2 months ago
2005
ACM
This paper studies the impact on energy efficiency and thermal behavior of design style and clock-gating style in queue and array structures. These structures are major sources of...
DAC
2006
ACM
14 years 2 months ago
2006
ACM
This paper investigates methods for clock skew minimization using buffer and wire sizing. First, a technique that significantly improves solution quality and stability of sequent...
FSE
2005
Springer
14 years 2 months ago
2005
Springer
In this paper we present a distinguisher targeting towards irregularly clocked filter generators. The attack is applied on the irregularly clocked stream cipher called LILI-II. LI...