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» Power system on a chip (PSoC)
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ISLPED
2005
ACM
147views Hardware» more  ISLPED 2005»
14 years 29 days ago
System level power and performance modeling of GALS point-to-point communication interfaces
Due to difficulties in distributing a single global clock signal over increasingly large chip areas, a globally asynchronous, locally synchronous design is considered a promising ...
Koushik Niyogi, Diana Marculescu
MICRO
2008
IEEE
126views Hardware» more  MICRO 2008»
13 years 7 months ago
Multicore Resource Management
UAL PRIVATE MACHINE ABSTRACTION WOULD ALLOW SOFTWARE POLICIES TO EXPLICITLY MANAGE MICROARCHITECTURE RESOURCES. VPM POLICIES, IMPLEMENTED PRIMARILY IN SOFTWARE, TRANSLATE APPLICATI...
Kyle J. Nesbit, Miquel Moretó, Francisco J....
ICES
2005
Springer
138views Hardware» more  ICES 2005»
14 years 28 days ago
A Flexible On-Chip Evolution System Implemented on a Xilinx Virtex-II Pro Device
Abstract. There have been introduced a number of systems with evolvable hardware on a single chip. To overcome the lack of flexibility in these systems, we propose a single-chip e...
Kyrre Glette, Jim Torresen
DATE
2009
IEEE
113views Hardware» more  DATE 2009»
14 years 2 months ago
MPSoCs run-time monitoring through Networks-on-Chip
—Networks-on-Chip (NoCs) have appeared as design strategy to overcome the limitations, in terms of scalability, efficiency, and power consumption of current buses. In this paper...
Leandro Fiorin, Gianluca Palermo, Cristina Silvano
ICCAD
2001
IEEE
86views Hardware» more  ICCAD 2001»
14 years 4 months ago
System-Level Exploration for Pareto-Optimal Configurations in Parameterized Systems-on-a-Chip
In this work, we provide a technique for efficiently exploring the configuration space of a parameterized system-on-a-chip (SOC) architecture to find all Pareto-optimal configurat...
Tony Givargis, Frank Vahid, Jörg Henkel