35 search results - page 1 / 7 » Power-Delay Modeling of Dynamic CMOS Gates for Circuit Optim... |
ICCAD
2001
IEEE
14 years 4 months ago
2001
IEEE
PATMOS
2005
Springer
14 years 28 days ago
2005
Springer
The time taken for a CMOS logic gate output to change after one or more inputs have changed is called the output delay of the gate. A conventional multi-input CMOS gate is designed...
VLSID
2003
IEEE
14 years 7 months ago
2003
IEEE
In the previous work, the problem of nding gate delays to eliminate glitches has been solved by linear programs (LP) requiring an exponentially large number ofconstraints. By intr...
DAC
1999
ACM
13 years 11 months ago
1999
ACM
Dynamic power consumed in CMOS gates goes down quadratically with the supply voltage. By maintaining a high supply voltage for gates on the critical path and by using a low supply...
DAC
2005
ACM
13 years 9 months ago
2005
ACM
Minimizing power consumption is one of the most important objectives in IC design. Resizing gates and assigning different Vt’s are common ways to meet power and timing budgets. ...