35 search results - page 2 / 7 » Power-Delay Modeling of Dynamic CMOS Gates for Circuit Optim... |
GLVLSI
2003
IEEE
14 years 22 days ago
2003
IEEE
—Interconnect inductance introduces a shielding effect which decreases the effective capacitance seen by the driver of a circuit, reducing the gate delay. A model of the effectiv...
ISQED
2008
IEEE
14 years 1 months ago
2008
IEEE
In this paper dual-K (DKCMOS) technology is proposed as a method for gate leakage power reduction. An integer linear programming (ILP) based algorithm is proposed for its optimiza...
ISLPED
1995
ACM
13 years 11 months ago
1995
ACM
We consider the problem of transistor sizing in a static CMOS layout to minimizethe power consumption of the circuit subject to a given delay constraint. Based on our characteriza...
ICCAD
2003
IEEE
14 years 4 months ago
2003
IEEE
This paper proposes an optimum methodology for assigning supply and threshold voltages to modules in a CMOS circuit such that the overall energy consumption is minimized for a giv...
ISQED
2005
IEEE
14 years 1 months ago
2005
IEEE
As technology continues to scale beyond 100nm, there is a significant increase in performance uncertainty of CMOS logic due to process and environmental variations. Traditional c...