86 search results - page 11 / 18 » Predictable Instruction Caching for Media Processors |
ICCD
2005
IEEE
14 years 5 months ago
2005
IEEE
Cache memories are commonly implemented through multiple memory banks to improve bandwidth and latency. The early knowledge of the data cache bank that an instruction will access ...
HPCA
2005
IEEE
14 years 8 months ago
2005
IEEE
Long-latency loads are critical in today's processors due to the ever-increasing speed gap with memory. Not only do these loads block the execution of dependent instructions,...
RTCSA
1999
IEEE
14 years 21 days ago
1999
IEEE
In this paper we present a technique for Worst-Case Execution Time WCET analysis for pipelined processors. Our technique uses a standard simulator instead of special-purpose pipel...
MICRO
1999
IEEE
14 years 21 days ago
1999
IEEE
This paper studies an interesting yet less explored behavior of memory access instructions, called access region locality. Unlike the traditional temporal and spatial data localit...
WMPI
2004
ACM
14 years 1 months ago
2004
ACM
High-performance out-of-order processors spend a significant portion of their execution time on the incorrect program path even though they employ aggressive branch prediction al...