Sciweavers

44 search results - page 1 / 9
» Prefetching for improved bus wrapper performance in cores
Sort
View
TODAES
2002
45views more  TODAES 2002»
13 years 7 months ago
Prefetching for improved bus wrapper performance in cores
Roman L. Lysecky, Frank Vahid
ISSS
2000
IEEE
88views Hardware» more  ISSS 2000»
13 years 12 months ago
Experiments with the Peripheral Virtual Component Interface
The Peripheral Virtual Component Interface, or PVCI, is a standard intended to simplify the interfacing of peripheral cores to on-chip buses in a system-on-a-chip, by standardizin...
Roman L. Lysecky, Frank Vahid, Tony Givargis
DATE
2000
IEEE
88views Hardware» more  DATE 2000»
13 years 12 months ago
Techniques for Reducing Read Latency of Core Bus Wrappers
Today’s system-on-a-chip designs consist of many cores. To enable cores to be easily integrated into different systems, many propose creating cores with their internal logic sep...
Roman L. Lysecky, Frank Vahid, Tony Givargis
MICRO
2009
IEEE
134views Hardware» more  MICRO 2009»
14 years 2 months ago
Coordinated control of multiple prefetchers in multi-core systems
Aggressive prefetching is very beneficial for memory latency tolerance of many applications. However, it faces significant challenges in multi-core systems. Prefetchers of diff...
Eiman Ebrahimi, Onur Mutlu, Chang Joo Lee, Yale N....
IEEEPACT
2005
IEEE
14 years 1 months ago
Future Execution: A Hardware Prefetching Technique for Chip Multiprocessors
This paper proposes a new hardware technique for using one core of a CMP to prefetch data for a thread running on another core. Our approach simply executes a copy of all non-cont...
Ilya Ganusov, Martin Burtscher