44 search results - page 2 / 9 » Prefetching for improved bus wrapper performance in cores |
PPOPP
2009
ACM
14 years 8 months ago
2009
ACM
Data prefetching has been widely used in the past as a technique for hiding memory access latencies. However, data prefetching in multi-threaded applications running on chip multi...
MICRO
2008
IEEE
14 years 1 months ago
2008
IEEE
Existing DRAM controllers employ rigid, non-adaptive scheduling and buffer management policies when servicing prefetch requests. Some controllers treat prefetch requests the same ...
ISPDC
2010
IEEE
13 years 6 months ago
2010
IEEE
—Super-scalar, out-of-order processors that can have tens of read and write requests in the execution window place significant demands on Memory Level Parallelism (MLP). Multi- ...
DATE
2003
IEEE
14 years 24 days ago
2003
IEEE
The performance of a system, especially a multiprocessor system, heavily depends upon the efficiency of its bus architecture. This paper presents a methodology to generate a custo...
DAC
2005
ACM
13 years 9 months ago
2005
ACM
This paper presents a new method for designing test wrappers for embedded cores with multiple clock domains. By exploiting the use of multiple shift frequencies, the proposed meth...