This paper describes the Amorphous FPGA, an innovative architecture attempting to optimally allocate logic and routing resource on per-mapping basis. Designed for high performance...
Rapid approximation of the transient response of high-speed global interconnects is needed to estimate the time delay, crosstalk, and overshoot in a GSI multilevel wiring network....
Raguraman Venkatesan, Jeffrey A. Davis, James D. M...
500+ MHz designs using deep-submicron (DSM) copper interconnects require accurate and efficient modeling of cladding-metals’ frequency-dependent impedance [1]. In this paper, fo...
In this paper we use a general procedure for fractional integration and structural breaks at unknown points in time, which allows for different orders of integration and determini...
— As Double Patterning Technology (DPT) becomes the only solution for 32-nm lithography process, we need to investigate how DPT affects the performance of a chip. In this paper, ...