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DATE
2010
IEEE
154views Hardware» more  DATE 2010»
13 years 8 months ago
Computing robustness of FlexRay schedules to uncertainties in design parameters
Abstract--In the current environment of rapidly changing invehicle requirements and ever-increasing functional content for automotive EE systems, there are several sources of uncer...
Arkadeb Ghosal, Haibo Zeng, Marco Di Natale, Yakov...
ISSS
1995
IEEE
161views Hardware» more  ISSS 1995»
13 years 11 months ago
Synthesis of pipelined DSP accelerators with dynamic scheduling
To construct complete systems on silicon, application speci c DSP accelerators are needed to speed up the execution of high throughput DSP algorithms. In this paper, a methodology...
Patrick Schaumont, Bart Vanthournout, Ivo Bolsens,...
DATE
2005
IEEE
154views Hardware» more  DATE 2005»
14 years 1 months ago
A Time Slice Based Scheduler Model for System Level Design
Efficient evaluation of design choices, in terms of selection of algorithms to be implemented as hardware or software, and finding an optimal hw/sw design mix is an important re...
Luciano Lavagno, Claudio Passerone, Vishal Shah, Y...
CODES
2009
IEEE
14 years 2 months ago
A variation-tolerant scheduler for better than worst-case behavioral synthesis
– There has been a recent shift in design paradigms, with many turning towards yield-driven approaches to synthesize and design systems. A major cause of this shift is the contin...
Jason Cong, Albert Liu, Bin Liu
CODES
2005
IEEE
14 years 1 months ago
Conflict analysis in multiprocess synthesis for optimized system integration
This paper presents a novel approach for multiprocess synthesis supporting well-tailored module integration at system level. The goal is to extend the local scope of existing arch...
Oliver Bringmann, Wolfgang Rosenstiel, Axel Sieben...