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» Process Variations and their Impact on Circuit Operation
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ISVLSI
2006
IEEE
129views VLSI» more  ISVLSI 2006»
14 years 1 months ago
Dependability Analysis of Nano-scale FinFET circuits
FinFET technology has been proposed as a promising alternative for deep sub-micro bulk CMOS technology, because of its better scalability. Previous work have studied the performan...
Feng Wang 0004, Yuan Xie, Kerry Bernstein, Yan Luo
DATE
2010
IEEE
161views Hardware» more  DATE 2010»
14 years 13 days ago
Aging-resilient design of pipelined architectures using novel detection and correction circuits
—Time-dependent performance degradation due to transistor aging caused by mechanisms such as Negative Bias Temperature Instability (NBTI) and Hot Carrier Injection (HCI) is one o...
Hamed F. Dadgour, Kaustav Banerjee
DAC
1994
ACM
13 years 11 months ago
Statistical Delay Modeling in Logic Design and Synthesis
Manufacturing disturbances are inevitable in the fabrication of integrated circuits. These disturbances will result in variations in the delay speci cations of manufactured circui...
Horng-Fei Jyu, Sharad Malik
ASPDAC
2009
ACM
161views Hardware» more  ASPDAC 2009»
14 years 1 months ago
Risk aversion min-period retiming under process variations
— Recent advances in statistical timing analysis (SSTA) achieve great success in computing arrival times under variations by extending sum and maximum operations to random variab...
Jia Wang, Hai Zhou
DATE
2005
IEEE
143views Hardware» more  DATE 2005»
13 years 9 months ago
Statistical Modeling of Pipeline Delay and Design of Pipeline under Process Variation to Enhance Yield in sub-100nm Technologies
Operating frequency of a pipelined circuit is determined by the delay of the slowest pipeline stage. However, under statistical delay variation in sub-100nm technology regime, the...
Animesh Datta, Swarup Bhunia, Saibal Mukhopadhyay,...