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» Process variation aware cache leakage management
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DATE
2007
IEEE
100views Hardware» more  DATE 2007»
14 years 2 months ago
Working with process variation aware caches
Deep-submicron designs have to take care of process variation effects as variations in critical process parameters result in large variations in access latencies of hardware compo...
Madhu Mutyam, Narayanan Vijaykrishnan
DATE
2009
IEEE
131views Hardware» more  DATE 2009»
14 years 3 months ago
Process Variation Aware SRAM/Cache for aggressive voltage-frequency scaling
this paper proposes a novel Process Variation Aware SRAM architecture designed to inherently support voltage scaling. The peripheral circuitry of the SRAM is modified to selectivel...
Avesta Sasan, Houman Homayoun, Ahmed M. Eltawil, F...
ASPDAC
2007
ACM
98views Hardware» more  ASPDAC 2007»
13 years 10 months ago
A Software Technique to Improve Yield of Processor Chips in Presence of Ultra-Leaky SRAM Cells Caused by Process Variation
- Exceptionally leaky transistors are increasingly more frequent in nano-scale technologies due to lower threshold voltage and its increased variation. Such leaky transistors may e...
Maziar Goudarzi, Tohru Ishihara, Hiroto Yasuura
DATE
2008
IEEE
119views Hardware» more  DATE 2008»
14 years 3 months ago
Process Variation Aware Issue Queue Design
In sub-90nm process technology it becomes harder to control the fabrication process, which in turn causes variations between the design-time parameters and the fabricated paramete...
Raghavendra K, Madhu Mutyam
MICRO
2007
IEEE
144views Hardware» more  MICRO 2007»
14 years 2 months ago
Process Variation Tolerant 3T1D-Based Cache Architectures
Process variations will greatly impact the stability, leakage power consumption, and performance of future microprocessors. These variations are especially detrimental to 6T SRAM ...
Xiaoyao Liang, Ramon Canal, Gu-Yeon Wei, David Bro...