41 search results - page 6 / 9 » Process variation aware clock tree routing |
INFOCOM
2010
IEEE
13 years 5 months ago
2010
IEEE
—Upon the occurrence of a phenomenon of interest in a wireless sensor network, multiple sensors may be activated, leading to data implosion and redundancy. Data aggregation and/o...
ASPDAC
2010
ACM
13 years 5 months ago
2010
ACM
Abstract--In nanometer-scale VLSI physical design, clock network becomes a major concern on determining the total performance of digital circuit. Clock skew and PVT (Process, Volta...
ICCAD
1999
IEEE
13 years 11 months ago
1999
IEEE
We consider the problem of finding an optimal clock schedule, i.e. optimal arrival times for clock signals at latches of a VLSI chip. We describe a general model which includes al...
ICCAD
2010
IEEE
13 years 5 months ago
2010
IEEE
Clock skew minimization has been an important design constraint. However, due to the complexity of Process, Voltage, and Temperature (PVT) variations, the minimization of clock sk...
ACSD
2005
IEEE
14 years 1 months ago
2005
IEEE
We present a bundled data communication scheme that is robust to crosstalk effects, and to manufacturing and environmental variations. Unlike a data bus, where each receiver alway...