63 search results - page 7 / 13 » Process variation robust clock tree routing |
ICCAD
2010
IEEE
13 years 5 months ago
2010
IEEE
Clock mesh is popular in high performance VLSI design because it is more robust against variations than clock tree at a cost of higher power consumption. In this paper, we propose ...
ICIP
2006
IEEE
14 years 1 months ago
2006
IEEE
—In this paper, we propose multiple tree construction schemes and routing protocols for video streaming over wireless ad hoc networks. The basic idea is to split the video into m...
DAC
2006
ACM
14 years 1 months ago
2006
ACM
This paper investigates methods for clock skew minimization using buffer and wire sizing. First, a technique that significantly improves solution quality and stability of sequent...
ICCAD
1999
IEEE
13 years 12 months ago
1999
IEEE
We consider the problem of finding an optimal clock schedule, i.e. optimal arrival times for clock signals at latches of a VLSI chip. We describe a general model which includes al...
ICCAD
2010
IEEE
13 years 5 months ago
2010
IEEE
Clock skew minimization has been an important design constraint. However, due to the complexity of Process, Voltage, and Temperature (PVT) variations, the minimization of clock sk...