1136 search results - page 24 / 228 » Processing-in-Memory: Exploring the Design Space |
119
Voted
HPCA
2006
IEEE
16 years 3 months ago
2006
IEEE
This paper explores the multi-dimensional design space for chip multiprocessors, exploring the inter-related variables of core count, pipeline depth, superscalar width, L2 cache s...
115
Voted
CODES
2007
IEEE
15 years 10 months ago
2007
IEEE
High-end biomedical applications are a good target for specificpurpose system-on-chip (SoC) implementations. Human heart electrocardiogram (ECG) real-time monitoring and analysis ...
129
Voted
DATE
2009
IEEE
15 years 10 months ago
2009
IEEE
- In this paper, we present a design methodology for automatic platform generation of future heterogeneous systems where communication happens via the Network-onChip (NoC) approach...
ASPDAC
2006
ACM
15 years 9 months ago
2006
ACM
- Chip floorplan in a reticle for Multi-Project Wafer (MPW) plays a key role in deciding chip fabrication cost. In this paper1 , we propose a methodology to explore reticle floopla...
156
Voted
ESTIMEDIA
2003
Springer
15 years 8 months ago
2003
Springer
— The constant increase in levels of integration and the reduction of the time-to-market have led to the definition of new methodologies stressing reuse. This involves not only ...