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» Processor Architectures for Ontogenesis
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HPCA
1999
IEEE
15 years 8 months ago
Improving the Accuracy vs. Speed Tradeoff for Simulating Shared-Memory Multiprocessors with ILP Processors
Previous simulators for shared-memory architectures have imposed a large tradeoff between simulation accuracy and speed. Most such simulators model simple processors that do not e...
Murthy Durbhakula, Vijay S. Pai, Sarita V. Adve
ARCS
2008
Springer
15 years 6 months ago
Hybrid Parallel Sort on the Cell Processor
: Sorting large data sets has always been an important application, and hence has been one of the benchmark applications on new parallel architectures. We present a parallel sortin...
Jörg Keller, Christoph W. Kessler, Kalle K&ou...
ENTCS
2006
144views more  ENTCS 2006»
15 years 4 months ago
Contorsion: A Semantic XPath Processor
This work describes the architecture of Contorsion, a semantic XPath processor that acts over an RDF mapping of XML. It contributes to a recent research trend that defines an XML-...
Rubén Tous, Jaime Delgado
DAC
2001
ACM
16 years 5 months ago
Testing for Interconnect Crosstalk Defects Using On-Chip Embedded Processor Cores
Crosstalk effects degrade the integrity of signals traveling on long interconnects and must be addressed during manufacturing testing. External testing for crosstalk is expensive ...
Li Chen, Xiaoliang Bai, Sujit Dey
HPCA
2001
IEEE
16 years 4 months ago
Data-Flow Prescheduling for Large Instruction Windows in Out-of-Order Processors
The performance of out-of-order processors increases with the instruction window size. In conventional processors, the effective instruction window cannot be larger than the issue...
Pierre Michaud, André Seznec