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» Processor Architectures for Ontogenesis
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ISSS
1995
IEEE
100views Hardware» more  ISSS 1995»
15 years 7 months ago
Optimal code generation for embedded memory non-homogeneous register architectures
This paper examines the problem of code-generation for expression trees on non-homogeneous register set architectures. It proposes and proves the optimality of an O(n) algorithm f...
Guido Araujo, Sharad Malik
OOPSLA
2010
Springer
15 years 2 months ago
Towards a tool-based development methodology for sense/compute/control applications
This poster presents a design language and a tool suite covering the development life-cycle of a Sense/Compute/Control (SCC) application. This language makes it possible to define...
Damien Cassou, Julien Bruneau, Julien Mercadal, Qu...
LCPC
2005
Springer
15 years 9 months ago
Compiler Supports and Optimizations for PAC VLIW DSP Processors
Abstract. Compiler is substantially regarded as the most essential component in the software toolchain to promote a successful processor design. This paper describes our preliminar...
Yung-Chia Lin, Chung-Lin Tang, Chung-Ju Wu, Ming-Y...
TVLSI
2010
14 years 10 months ago
A Low-Power DSP for Wireless Communications
This paper proposes a low-power high-throughput digital signal processor (DSP) for baseband processing in wireless terminals. It builds on our earlier architecture--Signal processi...
Hyunseok Lee, Chaitali Chakrabarti, Trevor N. Mudg...
VLSID
2002
IEEE
174views VLSI» more  VLSID 2002»
16 years 4 months ago
Architecture Implementation Using the Machine Description Language LISA
The development of application specific instruction set processors comprises several design phases: architecture exploration, software tools design, system verification and design...
Oliver Schliebusch, Andreas Hoffmann, Achim Nohl, ...