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FPL
2008
Springer
119views Hardware» more  FPL 2008»
13 years 10 months ago
An FPGA-based high-speed, low-latency trigger processor for high-energy physics
An example of an FPGA based application for a high-energy physics experiment is presented which features all facets of modern FPGA design. The special requirements here are high b...
Jan de Cuveland, Felix Rettig, Venelin Angelov, Vo...
TVLSI
2008
85views more  TVLSI 2008»
13 years 9 months ago
Low-Complexity Policies for Energy-Performance Tradeoff in Chip-Multi-Processors
Chip-Multi-Processors (CMP) utilize multiple energy-efficient Processing Elements (PEs) to deliver high performance while maintaining an efficient ratio of performance to energy-c...
A. Elyada, Ran Ginosar, Uri Weiser
DATE
2010
IEEE
108views Hardware» more  DATE 2010»
13 years 6 months ago
Performance-asymmetry-aware topology virtualization for defect-tolerant NoC-based many-core processors
Topology virtualization techniques are proposed for NoCbased many-core processors with core-level redundancy to isolate hardware changes caused by on-chip defective cores. Prior w...
Lei Zhang 0008, Yue Yu, Jianbo Dong, Yinhe Han, Sh...
DFT
2009
IEEE
178views VLSI» more  DFT 2009»
14 years 4 months ago
Soft Core Embedded Processor Based Built-In Self-Test of FPGAs
This paper presents the first implementation of Built-In Self-Test (BIST) of Field Programmable Gate Arrays (FPGAs) using a soft core embedded processor for reconfiguration of the...
Bradley F. Dutton, Charles E. Stroud
FPGA
2000
ACM
145views FPGA» more  FPGA 2000»
14 years 25 days ago
A C compiler for a processor with a reconfigurable functional unit
This paper describes a C compiler for a mixed Processor/FPGA architecture where the FPGA is a Reconfigurable Functional Unit (RFU). It presents three compilation techniques that c...
Zhi Alex Ye, U. Nagaraj Shenoy, Prithviraj Banerje...