113 search results - page 16 / 23 » Prototypes for Automated Architectural 3D-Layout |
DAC
1999
ACM
14 years 10 months ago
1999
ACM
This paper describes a novel methodology for high performance asynchronous design based on timed circuits and on CAD support for their synthesis using Relative Timing. This method...
DAC
2001
ACM
14 years 10 months ago
2001
ACM
In this paper, we present a new technique for the e cient dynamic detection and removal of inactive clauses, i.e. clauses that do not a ect the solutions of interest of a Boolean ...
DAC
2002
ACM
14 years 10 months ago
2002
ACM
A central problem in functional verification is to check that a circuit block is producing correct outputs while enforcing that the environment is providing legal inputs. To attac...
DAC
2003
ACM
14 years 10 months ago
2003
ACM
Binary Decision Diagrams (BDDs) often fail to exploit sharing between Boolean functions that differ only in their support variables. In a memory circuit, for example, the function...
DAC
2003
ACM
14 years 10 months ago
2003
ACM
This paper describes a case study and design flow of a secure embedded system called ThumbPod, which uses cryptographic and biometric signal processing acceleration. It presents t...