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» Pseudo-Exhaustive Testing of Sequential Circuits
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ICCAD
2000
IEEE
77views Hardware» more  ICCAD 2000»
14 years 9 days ago
Improving the Proportion of At-Speed Tests in Scan BIST
A method to select the lengths of functional sequences in a BIST scheme for scan designs is proposed in this paper. A functional sequence is a sequence of primary input vectors ap...
Yu Huang, Irith Pomeranz, Sudhakar M. Reddy, Janus...
ICCAD
1997
IEEE
144views Hardware» more  ICCAD 1997»
14 years 3 days ago
Partial scan delay fault testing of asynchronous circuits
Asynchronous circuits operate correctly only under timing assumptions. Hence testing those circuits for delay faults is crucial. This paper describes a three-step method to detect...
Michael Kishinevsky, Alex Kondratyev, Luciano Lava...
ICCAD
1995
IEEE
94views Hardware» more  ICCAD 1995»
13 years 11 months ago
Test register insertion with minimum hardware cost
Implementing a built-in self-test by a "test per clock" scheme offers advantages concerning fault coverage, detection of delay faults, and test application time. Such a ...
Albrecht P. Stroele, Hans-Joachim Wunderlich
DAC
1994
ACM
13 years 12 months ago
Functional Test Generation for FSMs by Fault Extraction
Recent results indicate that functional test pattern generation (TPG) techniques may provide better defect coverages than do traditional logic-level techniques. Functional TPG alg...
Bapiraju Vinnakota, Jason Andrews
DATE
2007
IEEE
138views Hardware» more  DATE 2007»
14 years 2 months ago
An ADC-BiST scheme using sequential code analysis
This paper presents a built-in self-test (BiST) scheme for analog to digital converters (ADC) based on a linear ramp generator and efficient output analysis. The proposed analysi...
Erdem Serkan Erdogan, Sule Ozev