5 search results - page 1 / 1 » Pseudo-random clocking to enhance signal integrity |
SOCC
2008
IEEE
14 years 5 months ago
2008
IEEE
— A methodology is proposed to reduce power/ground and substrate coupling noise by randomizing the clock signal. A pseudo-random number generation algorithm is used to produce a ...
DATE
2009
IEEE
14 years 5 months ago
2009
IEEE
—Partial Reconfiguration (PR) of FPGAs presents many opportunities for application design flexibility, enabling tasks to dynamically swap in and out of the FPGA without entire sy...
ASPDAC
2007
ACM
14 years 2 months ago
2007
ACM
This paper presents a design methodology that was applied to the design of a 2.4GHz dual-core SPARC64TM microprocessor with 90nm CMOS technology. It focuses on the newly adopted t...
SLIP
2004
ACM
14 years 4 months ago
2004
ACM
Throughput, power consumption, signal integrity, pin count and routing complexity are all increasingly important interconnect issues that the system designer must deal with. Recen...
ICCAD
1997
IEEE
14 years 2 months ago
1997
IEEE
The relentless push for high performance in custom digital circuits has led to renewed emphasis on circuit optimization or tuning. The parameters of the optimization are typically...