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» Quantifying Instruction Criticality
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ASAP
2005
IEEE
133views Hardware» more  ASAP 2005»
14 years 1 months ago
Speedups from Partitioning Critical Software Parts to Coarse-Grain Reconfigurable Hardware
In this paper, we propose a hardware/software partitioning method for improving applications’ performance in embedded systems. Critical software parts are accelerated on hardwar...
Michalis D. Galanis, Grigoris Dimitroulakos, Costa...
GLVLSI
2006
IEEE
142views VLSI» more  GLVLSI 2006»
14 years 1 months ago
Dynamic instruction schedulers in a 3-dimensional integration technology
We present the design of high-performance and energy-efficient dynamic instruction schedulers in a 3-Dimensional integration technology. Based on a previous observation that the c...
Kiran Puttaswamy, Gabriel H. Loh
ISCA
2005
IEEE
134views Hardware» more  ISCA 2005»
14 years 1 months ago
An Architecture Framework for Transparent Instruction Set Customization in Embedded Processors
Instruction set customization is an effective way to improve processor performance. Critical portions of application dataflow graphs are collapsed for accelerated execution on s...
Nathan Clark, Jason A. Blome, Michael L. Chu, Scot...
MICRO
2003
IEEE
95views Hardware» more  MICRO 2003»
14 years 20 days ago
Processor Acceleration Through Automated Instruction Set Customization
Application-specific extensions to the computational capabilities of a processor provide an efficient mechanism to meet the growing performance and power demands of embedded appl...
Nathan Clark, Hongtao Zhong, Scott A. Mahlke
HPCA
2001
IEEE
14 years 7 months ago
Speculative Data-Driven Multithreading
Mispredicted branches and loads that miss in the cache cause the majority of retirement stalls experienced by sequential processors; we call these critical instructions. Despite t...
Amir Roth, Gurindar S. Sohi