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WSC
1997
13 years 9 months ago
Applications of the Universal Joint Task List to Joint Exercise Results
The foundation of readiness is training. The Chairman, Joint Chiefs of Staff (CJCS) Joint Training Program institutes methods for identifying training requirements through review ...
Sam H. Parry, Michael C. McAneny, Richard J. Drome...
ATVA
2007
Springer
136views Hardware» more  ATVA 2007»
14 years 2 months ago
Symbolic Fault Tree Analysis for Reactive Systems
Fault tree analysis is a traditional and well-established technique for analyzing system design and robustness. Its purpose is to identify sets of basic events, called cut sets, wh...
Marco Bozzano, Alessandro Cimatti, Francesco Tappa...
DATE
2010
IEEE
180views Hardware» more  DATE 2010»
14 years 1 months ago
Reliability- and process variation-aware placement for FPGAs
Abstract—Negative bias temperature instability (NBTI) significantly affects nanoscale integrated circuit performance and reliability. The degradation in threshold voltage (Vth) d...
Assem A. M. Bsoul, Naraig Manjikian, Li Shang
CODES
2006
IEEE
14 years 2 months ago
Integrated analysis of communicating tasks in MPSoCs
Predicting timing behavior is key to efficient embedded real-time system design and verification. Especially memory accesses and co-processor calls over shared communication net...
Simon Schliecker, Matthias Ivers, Rolf Ernst
ICCAD
2002
IEEE
141views Hardware» more  ICCAD 2002»
14 years 4 months ago
A hierarchical modeling framework for on-chip communication architectures
— The communication sub-system of complex IC systems is increasingly critical for achieving system performance. Given this, it is important that the on-chip communication archite...
Xinping Zhu, Sharad Malik