Sciweavers

694 search results - page 85 / 139
» Quantum associative memory
Sort
View
SIGMETRICS
1997
ACM
111views Hardware» more  SIGMETRICS 1997»
14 years 27 days ago
Cache Behavior of Network Protocols
In this paper we present a performance study of memory reference behavior in network protocol processing, using an Internet-based protocol stack implemented in the x-kernel runnin...
Erich M. Nahum, David J. Yates, James F. Kurose, D...
INFORMS
1998
142views more  INFORMS 1998»
13 years 8 months ago
Distributed State Space Generation of Discrete-State Stochastic Models
High-level formalisms such as stochastic Petri nets can be used to model complex systems. Analysis of logical and numerical properties of these models often requires the generatio...
Gianfranco Ciardo, Joshua Gluckman, David M. Nicol
DAC
2008
ACM
14 years 9 months ago
Miss reduction in embedded processors through dynamic, power-friendly cache design
Today, embedded processors are expected to be able to run complex, algorithm-heavy applications that were originally designed and coded for general-purpose processors. As a result...
Garo Bournoutian, Alex Orailoglu
PPOPP
2010
ACM
14 years 6 months ago
Data transformations enabling loop vectorization on multithreaded data parallel architectures
Loop vectorization, a key feature exploited to obtain high performance on Single Instruction Multiple Data (SIMD) vector architectures, is significantly hindered by irregular memo...
Byunghyun Jang, Perhaad Mistry, Dana Schaa, Rodrig...
ICCD
2007
IEEE
146views Hardware» more  ICCD 2007»
14 years 5 months ago
Exploring DRAM cache architectures for CMP server platforms
As dual-core and quad-core processors arrive in the marketplace, the momentum behind CMP architectures continues to grow strong. As more and more cores/threads are placed on-die, ...
Li Zhao, Ravi R. Iyer, Ramesh Illikkal, Donald New...