214 search results - page 19 / 43 » Quasi-Resonant Interconnects: A Low Power Design Methodology |
HPCA
2009
IEEE
14 years 8 months ago
2009
IEEE
Performance and power consumption of an on-chip interconnect that forms the backbone of Chip Multiprocessors (CMPs), are directly influenced by the underlying network topology. Bo...
DATE
2006
IEEE
14 years 1 months ago
2006
IEEE
— Clock power consumes a significant fraction of total power dissipation in high speed precharge/evaluate logic styles. In this paper, we present a novel low-cost design methodol...
VTS
2005
IEEE
14 years 1 months ago
2005
IEEE
An automated design procedure is described for synthesizing circuits with low power concurrent error detection. It is based on pre-synthesis selection of a parity-check code follo...
VLSID
2005
IEEE
14 years 8 months ago
2005
IEEE
This paper presents two schemes for the implementation of high performance and low power FIR filtering Intellectual Property (IP) cores. Low power is achieved through the utilizat...
CODES
2003
IEEE
14 years 1 months ago
2003
IEEE
In this paper, we describe a new methodology based on game theory for minimizing the average power of a circuit during scheduling in behavioral synthesis. The problem of schedulin...