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» Quasi-Resonant Interconnects: A Low Power Design Methodology
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GLVLSI
2009
IEEE
112views VLSI» more  GLVLSI 2009»
14 years 2 months ago
Simultaneous shield and repeater insertion
Resource based optimization for high performance integrated circuits is presented. The methodology is applied to simultaneous shield and repeater insertion, resulting in minimum c...
Renatas Jakushokas, Eby G. Friedman
ISLPED
2005
ACM
99views Hardware» more  ISLPED 2005»
14 years 1 months ago
A low-power bus design using joint repeater insertion and coding
In this paper, we propose joint repeater insertion and crosstalk avoidance coding as a low-power alternative to repeater insertion for global bus design in nanometer technologies....
Srinivasa R. Sridhara, Naresh R. Shanbhag
DATE
1999
IEEE
129views Hardware» more  DATE 1999»
14 years 7 days ago
Battery-Powered Digital CMOS Design
In this paper, we consider the problem of maximizing the battery life (or duration of service) in battery-powered CMOS circuits. We first show that the battery efficiency (or utili...
Massoud Pedram, Qing Wu
ASPLOS
2006
ACM
13 years 11 months ago
Accurate and efficient regression modeling for microarchitectural performance and power prediction
We propose regression modeling as an efficient approach for accurately predicting performance and power for various applications executing on any microprocessor configuration in a...
Benjamin C. Lee, David M. Brooks
COMPUTER
2002
129views more  COMPUTER 2002»
13 years 7 months ago
Networks on Chips: A New SoC Paradigm
of abstraction and coarse granularity and distributed communication control. Focusing on using probabilistic metrics such as average values or variance to quantify design objective...
Luca Benini, Giovanni De Micheli