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IESS
2007
Springer
124views Hardware» more  IESS 2007»
15 years 11 months ago
Integrated Coupling and Clock Frequency Assignment of Accelerators During Hardware/Software Partitioning
: Hardware/software partitioning moves software kernels from a microprocessor to custom hardware accelerators. We consider advanced implementation options for accelerators, greatly...
Scott Sirowy, Frank Vahid
ASAP
2003
IEEE
153views Hardware» more  ASAP 2003»
15 years 10 months ago
Hardware Synthesis for Multi-Dimensional Time
This paper introduces basic principles for extending the classical systolic synthesis methodology to multi-dimensional time. Multi-dimensional scheduling enables complex algorithm...
Anne-Claire Guillou, Patrice Quinton, Tanguy Risse...
148
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FPL
1999
Springer
103views Hardware» more  FPL 1999»
15 years 9 months ago
IP Validation for FPGAs Using Hardware Object Technology
Although verification and simulation tools are always improving, the results they provide remain hard to analyze and interpret. On one hand, verification sticks to the functional ...
Steve Casselman, John Schewel, Christophe Beaumont
EURODAC
1994
IEEE
117views VHDL» more  EURODAC 1994»
15 years 8 months ago
A hardware environment for prototyping and partitioning based on multiple FPGAs
This paper presents a multiple-FPGA-based experimentation board. The problem to be solved is that of implementing a circuit into a set of FPGAs. This board provides a hardware env...
Marc Wendling, Wolfgang Rosenstiel
FPL
2000
Springer
116views Hardware» more  FPL 2000»
15 years 8 months ago
High-Level Area and Performance Estimation of Hardware Building Blocks on FPGAs
Abstract. Field-programmable gate arrays (FPGAs) have become increasingly interesting in system design and due to the rapid technological progress ever larger devices are commercia...
Rolf Enzler, Tobias Jeger, Didier Cottet, Gerhard ...