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» Re-Examining the Use of Network-on-Chip as Test Access Mecha...
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DATE
2005
IEEE
110views Hardware» more  DATE 2005»
14 years 1 months ago
Test Time Reduction Reusing Multiple Processors in a Network-on-Chip Based Architecture
The increasing complexity and the short life cycles of embedded systems are pushing the current system-onchip designs towards a rapid increasing on the number of programmable proc...
Alexandre M. Amory, Marcelo Lubaszewski, Fernando ...
DATE
2004
IEEE
131views Hardware» more  DATE 2004»
13 years 11 months ago
Efficient Modular Testing of SOCs Using Dual-Speed TAM Architectures
The increasing complexity of system-on-chip (SOC) integrated circuits has spurred the development of versatile automatic test equipment (ATE) that can simultaneously drive differe...
Anuja Sehgal, Krishnendu Chakrabarty
MICRO
2007
IEEE
159views Hardware» more  MICRO 2007»
14 years 1 months ago
Software-Based Online Detection of Hardware Defects Mechanisms, Architectural Support, and Evaluation
As silicon process technology scales deeper into the nanometer regime, hardware defects are becoming more common. Such defects are bound to hinder the correct operation of future ...
Kypros Constantinides, Onur Mutlu, Todd M. Austin,...
DATE
2003
IEEE
96views Hardware» more  DATE 2003»
14 years 23 days ago
Time Domain Multiplexed TAM: Implementation and Comparison
One of the difficult problems which core-based systemon-chip (SoC) designs face is test access. For testing the cores in a SoC, a special mechanism is required, since they are no...
Zahra Sadat Ebadi, André Ivanov
APSEC
2005
IEEE
14 years 1 months ago
A Passive Test Oracle Using a Component's API
A test oracle is a mechanism that is used during testing to determine whether a software component behaves correctly or not. The test oracle problem is widely acknowledged in the ...
Rakesh Shukla, David A. Carrington, Paul A. Stroop...