174 search results - page 28 / 35 » Reclocking for high-level synthesis |
EUROMICRO
2006
IEEE
14 years 1 months ago
2006
IEEE
This paper presents the modeling paradigm for Integrated Modular Avionics Design MIMAD V0, which is an extensible component-oriented framework that enables high level models of sy...
AADEBUG
2005
Springer
14 years 1 months ago
2005
Springer
Reprogrammable hardware systems are traditionally very difficult to debug due to their high level of parallelism. In our solution to this problem, features are inserted into the u...
FPL
2004
Springer
14 years 26 days ago
2004
Springer
A previous study [1] demonstrates the advantages of replacing registers by FPGA embedded memories during the storage allocation phase of High-Level Synthesis. The trend in new FPGA...
FPL
2004
Springer
14 years 26 days ago
2004
Springer
Abstract. High level modeling tools make it possible to synthesize a high performance FPGA design directly from a Simulink model. Accurate estimates of the FPGA resources required ...
DATE
2002
IEEE
14 years 13 days ago
2002
IEEE
The design of application (-domain) specific instructionset processors (ASIPs), optimized for code size, has traditionally been accompanied by the necessity to program assembly, ...