Sciweavers

174 search results - page 3 / 35
» Reclocking for high-level synthesis
Sort
View
DAC
1999
ACM
14 years 9 months ago
Soft Scheduling in High Level Synthesis
In this paper, we establish a theoretical framework for a new concept of scheduling called soft scheduling. In contrasts to the traditional schedulers referred as hard schedulers,...
Jianwen Zhu, Daniel Gajski
DSD
2010
IEEE
162views Hardware» more  DSD 2010»
13 years 7 months ago
A Parallel for Loop Memory Template for a High Level Synthesis Compiler
—We propose a parametrized memory template for applications with parallel for loops. The template’s parameters reflect important trade-offs made during system design. The temp...
Craig Moore, Wim Meeus, Harald Devos, Dirk Strooba...
VTS
2007
IEEE
135views Hardware» more  VTS 2007»
14 years 2 months ago
High Level Synthesis of Degradable ASICs Using Virtual Binding
—As the complexity of the integrated circuits increases, they become more susceptible to manufacturing faults, decreasing the total process yield. Thus, it would be desirable to ...
Nima Honarmand, A. Shahabi, Hasan Sohofi, Maghsoud...
ASPDAC
2005
ACM
113views Hardware» more  ASPDAC 2005»
14 years 2 months ago
Scalable interprocedural register allocation for high level synthesis
Abstract— The success of classical high level synthesis has been limited by the complexity of the applications it can handle, typically not large enough to necessitate the depart...
Rami Beidas, Jianwen Zhu
RSP
2005
IEEE
164views Control Systems» more  RSP 2005»
14 years 2 months ago
High Level Synthesis for Data-Driven Applications
Abstract— John von Neumann proposed his famous architecture in a context where hardware was very expensive and bulky. His goal was to maximize functionality with minimal hardware...
Etienne Bergeron, Xavier Saint-Mleux, Marc Feeley,...