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» Reclocking for high-level synthesis

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ISSS
2002
IEEE

127views Hardware» more ISSS 2002»

Dynamic Common Sub-Expression Elimination during Scheduling in High-Level Synthesis

14 years 14 days ago

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We introduce a new approach, “Dynamic Common Sub-expression Elimination (CSE)”, that dynamically eliminates common sub- expressions based on new opportunities created during s...

Alexandru Nicolau, Nikil D. Dutt, Rajesh Gupta, Ni...

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VLSID
2001
IEEE

82views VLSI» more VLSID 2001»

High Level Synthesis Of Multi-Precision Data Flow Graphs

14 years 8 months ago

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Vikas Agrawal, Anand Pande, Mahesh Mehendale

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FDL
2007
IEEE

165views Natural Language Processing» more FDL 2007»

Automatic High Level Assertion Generation and Synthesis for Embedded System Design

14 years 1 months ago

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SystemVerilog encapsulates both design description and verification properties in one language and provides a unified environment for engineers who have the formidable challenge o...

Lun Li, Frank P. Coyle, Mitchell A. Thornton

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IPPS
2007
IEEE

115views Distributed And Parallel Com...» more IPPS 2007»

High-Level Synthesis of HW Tasks Targeting Run-Time Reconfigurable FPGAs

14 years 1 months ago