Search Sciweavers | Sciweavers

174 search results - page 7 / 35

» Reclocking for high-level synthesis

143

click to vote

ISSS
2002
IEEE

127views Hardware» more ISSS 2002»

Dynamic Common Sub-Expression Elimination during Scheduling in High-Level Synthesis

15 years 9 months ago

Download mesl.ucsd.edu

We introduce a new approach, “Dynamic Common Sub-expression Elimination (CSE)”, that dynamically eliminates common sub- expressions based on new opportunities created during s...

Alexandru Nicolau, Nikil D. Dutt, Rajesh Gupta, Ni...

claim paper

Read More »

104

click to vote

VLSID
2001
IEEE

82views VLSI» more VLSID 2001»

High Level Synthesis Of Multi-Precision Data Flow Graphs

16 years 4 months ago

Download eprints.iisc.ernet.in

Vikas Agrawal, Anand Pande, Mahesh Mehendale

claim paper

Read More »

169

click to vote

FDL
2007
IEEE

165views Natural Language Processing» more FDL 2007»

Automatic High Level Assertion Generation and Synthesis for Embedded System Design

15 years 10 months ago

Download lyle.smu.edu

SystemVerilog encapsulates both design description and verification properties in one language and provides a unified environment for engineers who have the formidable challenge o...

Lun Li, Frank P. Coyle, Mitchell A. Thornton

claim paper

Read More »

105

click to vote

IPPS
2007
IEEE

115views Distributed And Parallel Com...» more IPPS 2007»

High-Level Synthesis of HW Tasks Targeting Run-Time Reconfigurable FPGAs

15 years 10 months ago