174 search results - page 8 / 35 » Reclocking for high-level synthesis |
DATE
2002
IEEE
14 years 15 days ago
2002
IEEE
Optimizing power consumption at high-level is a critical step towards power-efficient digital system designs. This paper addresses the power management problem by scheduling a giv...
ASAP
2000
IEEE
13 years 12 months ago
2000
IEEE
GLVLSI
2000
IEEE
13 years 12 months ago
2000
IEEE
In this paper we present a novel and fast estimation technique that produces tight latency lower bounds for Data Flow Graphs representing time critical segments of the application...
ICCAD
2000
IEEE
13 years 12 months ago
2000
IEEE
VLSISP
2002
13 years 7 months ago
2002