230 search results - page 12 / 46 » Reconfigurable Fast Memory Management System Design for Appl... |
DATE
2010
IEEE
14 years 1 months ago
2010
IEEE
—In order to solve the challenges in processor design for the next generation wireless communication systems, this paper first proposes a system level design flow for communicati...
CANPC
1999
Springer
14 years 25 days ago
1999
Springer
Streamlining communication is key to achieving good performance in shared-memory parallel programs. While full hardware support for cache coherence generally offers the best perfo...
DATE
2009
IEEE
14 years 3 months ago
2009
IEEE
Multi-core architectures are increasingly being adopted in the design of emerging complex embedded systems. Key issues of designing such systems are on-chip interconnects, memory a...
FPL
2007
Springer
14 years 2 months ago
2007
Springer
The effect of kernel operations on cache optimisations in a soft-core reconfigurable system is important for dynamic cache switching design. Considering kernel operations changes ...
CC
2008
Springer
13 years 10 months ago
2008
Springer
Heterogeneous multi-core and streaming architectures such as the GPU, Cell, ClearSpeed, and Imagine processors have better power/ performance ratios and memory bandwidth than tradi...