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156
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DATE
2002
IEEE
15 years 10 months ago
2002
IEEE
: A new technique is presented in this paper to improve the efficiency of data scheduling for multi-context reconfigurable architectures targeting multimedia and DSP applications. ...
95
Voted
ASAP
2007
IEEE
15 years 9 months ago
2007
IEEE
Dynamic reconfiguration allows to selectively substitute blocks of logic at run-time in order to improve the area efficiency of a FPGA design. This paper presents the design of a ...
172
Voted
ISCAS
2005
IEEE
15 years 11 months ago
2005
IEEE
—This paper presents a memory-conscious mapping methodology of computational intensive applications on coarse-grain reconfigurable arrays. By exploiting the inherent abundant amo...
142
Voted
ASAP
2009
IEEE
15 years 9 months ago
2009
IEEE
157
Voted
EUROGP
2008
Springer
15 years 7 months ago
2008
Springer
A new class of FPGA-based accelerators is presented for Cartesian Genetic Programming (CGP). The accelerators contain a genetic engine which is reused in all applications. Candidat...