740 search results - page 14 / 148 » Recursive layout generation |
ICCAD
2008
IEEE
14 years 6 months ago
2008
IEEE
In double patterning lithography (DPL) layout decomposition for 45nm and below process nodes, two features must be assigned opposite colors (corresponding to different exposures)...
DAC
1996
ACM
14 years 1 months ago
1996
ACM
A novel methodology for circuit design and automatic layout generation is proposed for a class of mixed-signal circuits in presence of layout parasitics and substrate induced nois...
DATE
2000
IEEE
14 years 2 months ago
2000
IEEE
This paper presents a methodology towards synthesis of high performance analog circuits. Layout parasitics are estimated and compensated during circuit sizing. Physical layout con...
ACTAC
2005
13 years 9 months ago
2005
Propagating scattered context grammars are used to generate their sentences together with their parses--that is, the sequences of labels denoting productions whose use lead to the ...
EURODAC
1995
IEEE
14 years 1 months ago
1995
IEEE
This paper presents a performance-oriented placement and routing tool for field-programmable gate arrays. Using recursive geometric partitioning for simultaneous placement and glo...