30 search results - page 4 / 6 » Reduced Delay BCD Adder |
ARITH
2007
IEEE
14 years 2 months ago
2007
IEEE
Shrinking feature sizes gives more headroom for designers to extend the functionality of microprocessors. The IEEE 754R working group has revised the IEEE 754-1985 Standard for Bi...
DATE
2007
IEEE
14 years 2 months ago
2007
IEEE
Despite the progress of the last decades in electronic design automation, arithmetic circuits have always received way less attention than other classes of digital circuits. Logic...
ARITH
2003
IEEE
14 years 28 days ago
2003
IEEE
We propose a split array multiplier organized in a left-to-right leapfrog (LRLF) structure with reduced delay compared to conventional array multipliers. Moreover, the proposed de...
DATE
2008
IEEE
14 years 2 months ago
2008
IEEE
Multi-input addition is an important operation for many DSP and video processing applications. On FPGAs, multi-input addition has traditionally been implemented using trees of car...
ASYNC
1997
IEEE
13 years 12 months ago
1997
IEEE
The realisation of Delay-Insensitive (DI) asynchronous circuits with a CMOS ternary logic is described in this paper. The main advantage of temary logic is the easy realisation of...