135 search results - page 14 / 27 » Reducing Power Dissipation in SRAM during Test |
ICCD
2003
IEEE
14 years 28 days ago
2003
IEEE
Excessive switching activity during shift cycles in scan-based cores imposes considerable test power challenges. To ensure rapid and reliable test of SOCs, we propose a scan chain...
ICCD
2006
IEEE
14 years 4 months ago
2006
IEEE
—In this paper we propose the method of task merging and idle period clustering for dynamic power management (DPM) in a real-time system with multiple processing elements. We sho...
GLVLSI
2006
IEEE
14 years 1 months ago
2006
IEEE
This paper presents a minimum area, low-power driven clustering algorithm for coarse-grained, antifuse-based FPGAs under delay constraints. The algorithm accurately predicts logic...
FAST
2007
13 years 9 months ago
2007
Reducing power consumption for server computers is important, since increased energy usage causes increased heat dissipation, greater cooling requirements, reduced computational d...
ASPDAC
2001
ACM
13 years 11 months ago
2001
ACM
Power-efficient design requires reducing power dissipation in all parts of the design and during all stages of the design process subject to constraints on the system performance ...